In recent years, following downsizing of a memory cell in a DRAM (Dynamic Random Access Memory), a gate length of a memory cell transistor is inevitably reduced. However, if the gate length is smaller, then the short channel effect of the transistor disadvantageously becomes more conspicuous, and sub-threshold current is disadvantageously increased. Furthermore, if substrate concentration is increased to suppress the short channel effect and the increase of the sub-threshold current, junction leakage increases. Due to this, the DRAM is confronted with a serious problem of deterioration in refresh characteristics.
As a technique for avoiding the above-stated problem, attention has been paid to a fin field effect transistor (fin-FET) structured so that channel regions are formed to be thin each in the form of a fin in a perpendicular direction to a semiconductor substrate and so that gate electrodes are arranged around each of the channel regions, as disclosed in Japanese Patent Application National Publication No. 2006-501672 and Japanese Patent Application Laid-Open No. 2005-310921. The fin-FET is expected to be able to realize acceleration of operating rate, increase in ON-current, reduction in power consumption and the like, as compared with a planer transistor.
However, to suppress the short channel effect, it is necessary to make a channel width smaller than a gate length in the fin-FET.
FIG. 14A is a generally plan view of a conventional fin-FET. FIG. 14B is a generally plan view of a fin-FET according to a related art. FIG. 14A shows an active region 200a, gate regions 201a, and contact regions 202a in a standard fin-FET. FIG. 14B shows thinned contact regions, i.e., an active region 200b, gate regions 201b, and contact regions 202b. In FIG. 14B, the active region 200a shown in FIG. 14A is shown around the active region 200b by a broken line for comparison with FIG. 14A.
In FIG. 14A, the ON-current can be increased because the contact regions 202a can be secured to be sufficiently large. However, the short channel effect cannot be suppressed sufficiently because a channel width Wa is large, i.e., larger than a gate length Lga.
To solve the problem of the conventional fin-FET shown in FIG. 14A, there is proposed a method of narrowing a channel width Wb by forming the thinned active region 200b as shown in FIG. 14B. By doing so, a gate length Lgb is larger than the channel width Wb, so that the short channel effect can be suppressed. However, the fin-FET shown in FIG. 14B has the following problems. Not only the channel width Wb but also a width of each contact region 202b is narrowed. As a result, a contact resistance is increased and ON-current is reduced accordingly.